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Author Bergeron, Janick.

Title Writing Testbenches using System Verilog / by Janick Bergeron.

Imprint Boston, MA : Springer Science+Business Media, Inc., 2006.

Copies

Location Call No. OPAC Message Status
 Axe Books 24x7 Engineering E-Book  Electronic Book    ---  Available
Description 1 online resource (v.: digital)
text txt rdacontent
computer c rdamedia
online resource cr rdacarrier
Bibliography Includes bibliographical references and index.
Summary "Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and other SystemVerilog features are introduced within a coherent verification methodology and usage model." "Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog."--Jacket.
Subject Computer-aided design.
Computer engineering.
Engineering.
System safety.
Systems engineering.
Computer-aided design. (OCoLC)fst00872701
Computer engineering. (OCoLC)fst00872078
Engineering. (OCoLC)fst00910312
System safety. (OCoLC)fst01141421
Systems engineering. (OCoLC)fst01141455
Genre/Form Electronic books.
In: Springer e-books
Other Form: Print version: Bergeron, Janick. Writing testbenches using System Verilog. New York : Springer, 2006 (DLC) 2005938214
ISBN 9780387312750
0387312757
0387292217 (Cloth)
9780387292212 (Cloth)
Standard No. AU@ 000042134870
GBVCP 52499207X
NLGGC 384185886
NZ1 12050820

 
    
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