| Description |
1 online resource (viii, 240 pages) : illustrations |
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text txt rdacontent |
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computer c rdamedia |
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online resource cr rdacarrier |
| Series |
The Morgan Kaufmann series in systems on silicon |
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Morgan Kaufmann series in systems on silicon.
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| Bibliography |
Includes bibliographical references and index. |
| Summary |
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology. |
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Printbegrænsninger: Der kan printes kapitelvis. |
| Contents |
1. Introduction -- 2. Higher-Level Design Methodology and Associated Verification Problems -- 3. Basic Technology for Formal Verification -- 4. Verification Algorithms for FSM Models -- 5. Static Checking of Higher-Level Design Descriptions -- 6. Equivalence Checking on Higher-Level Design Descriptions -- 7. Model Checking on Higher-Level Design Descriptions -- 8. Simulation-Based Verification Techniques for System-Level Designs -- 9. Conclusion. |
| Note |
Print version record. |
| Language |
English. |
| Subject |
Systems on a chip -- Testing.
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Integrated circuits -- Verification.
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Formal methods (Computer science)
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Circuits intégrés -- Vérification.
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Méthodes formelles (Informatique)
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Integrated.
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.
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Systems on a chip -- Testing.
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Integrated circuits -- Verification.
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Formal methods (Computer science)
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Formal methods (Computer science)
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Integrated circuits -- Verification
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| Genre/Form |
dissertations.
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Academic theses
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Academic theses.
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Thèses et écrits académiques.
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| Added Author |
Ghosh, Indradeep, 1970-
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Prasad, Mukul.
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| Other Form: |
Print version: Fujita, Masahiro, 1956- Verification techniques for system-level design. Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008 9780123706164 0123706165 (DLC) 2007028038 (OCoLC)155126176 |
| ISBN |
9780080553139 (electronic bk.) |
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0080553133 (electronic bk.) |
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1281049646 |
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9781281049643 |
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9786611049645 |
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6611049649 |
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9780123706164 (pbk.) |
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0123706165 (pbk.) |
| Standard No. |
AU@ 000043178405 |
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AU@ 000051555307 |
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CHNEW 001007339 |
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DEBBG BV042305711 |
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DEBBG BV043091834 |
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DEBSZ 355395096 |
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DEBSZ 367750201 |
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DEBSZ 422169196 |
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GBVCP 802390501 |
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HEBIS 291468330 |
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NZ1 12541542 |
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NZ1 14540481 |
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NZ1 15189655 |
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