| Edition |
Second edition. |
| Description |
1 online resource |
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text txt rdacontent |
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computer c rdamedia |
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online resource cr rdacarrier |
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text file |
| Bibliography |
Includes bibliographical references and index. |
| Note |
Online resource; title from PDF title page (EBSCO, viewed July 13, 2017). |
| Summary |
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: Manufacturing techniques for 3-D ICs with TSVsElectrical modeling and closed-form expressions of through silicon viasSubstrate noise coupling in heterogeneous 3-D ICsDesign of 3-D ICs with inductive linksSynchronization in 3-D ICsVariation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires. |
| Note |
Copyright: Elsevier Science & Technology 2017 |
| Contents |
Front Cover -- Three-Dimensional Integrated Circuit Design -- Copyright Page -- Dedication -- Contents -- List of Figures -- About the Authors -- Preface to the Second Edition -- Preface to the First Edition -- Acknowledgments -- Organization of the Book -- 1 Introduction -- 1.1 Interconnect Issues in Integrated Systems -- 1.2 Three-Dimensional or Vertical Integration -- 1.2.1 Opportunities for Three-Dimensional Integration -- 1.2.2 Challenges of Three-Dimensional Integration -- 1.2.2.1 Technological/manufacturing limitations -- 1.2.2.2 Testing -- 1.2.2.3 Global interconnect design -- 1.2.2.4 Thermal issues -- 1.2.2.5 CAD algorithms and tools -- 1.3 Book Organization -- 2 Manufacturing of Three-Dimensional Packaged Systems -- 2.1 Stacking Methods for Transistors, Circuits, and Dies -- 2.1.1 System-in-Package -- 2.1.2 Transistor and Circuit Level Stacking -- 2.2 System-on-Package -- 2.3 Technologies for System-in-Package -- 2.3.1 Wire Bonded System-in-Package -- 2.3.2 Peripheral Vertical Interconnects -- 2.3.3 Area Array Vertical Interconnects -- 2.3.4 Metalizing the Walls of an SiP -- 2.4 Technologies for 2.5-D Integration -- 2.4.1 Interposer Materials -- 2.4.2 Metallization Processes -- 2.4.3 Vertical Interconnects -- 2.5 Summary -- 3 Manufacturing Technologies for Three-Dimensional Integrated Circuits -- 3.1 Monolithic Three-Dimensional ICs -- 3.1.1 Laser Crystallization -- 3.1.2 Seed Crystallization -- 3.1.3 Double-Gate Metal Oxide Semiconductor Field Effect Transistors for Stacked Three-Dimensional ICs -- 3.1.4 Molecular Bonding -- 3.2 Three-Dimensional ICs with Through Silicon Via or Intertier Via -- 3.2.1 Wafer Level Integration -- 3.2.2 Die-to-Die Integration -- 3.2.3 Bonding of Three-Dimensional ICs -- 3.3 Contactless Three-Dimensional ICs -- 3.3.1 Capacitively Coupled Three-Dimensional ICs. |
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3.3.2 Inductively Coupled Three-Dimensional ICs -- 3.4 Vertical Interconnects for Three-Dimensional ICs -- 3.5 Summary -- 4 Electrical Properties of Through Silicon Vias -- 4.1 Physical Characteristics of a Through Silicon Via -- 4.2 Electrical Model of Through Silicon Via -- 4.3 Modeling a Three-Dimensional Via as a Cylinder -- 4.4 Compact Models -- 4.4.1 Physical Parameters of Compact Resistance Models -- 4.4.1.1 Through silicon via resistance -- 4.4.1.2 High frequency effects -- 4.4.1.3 Effect of barrier thickness on resistivity -- 4.4.1.4 Temperature effect -- 4.4.2 Physical Parameters of Compact Inductance Models -- 4.4.2.1 Through silicon via inductance -- 4.4.2.2 Internal and external magnetic field -- 4.4.2.3 High frequency effects -- 4.4.2.4 Loop inductance -- 4.4.3 Physical Parameters of Compact Capacitance Models -- 4.4.3.1 Through silicon via capacitance -- 4.4.3.2 Through silicon via model including the effects of the depletion region -- 4.4.4 Physical Parameters of Compact Conductance Models -- 4.4.4.1 Through silicon via conductance -- 4.5 Through Silicon Via Impedance Models -- 4.5.1 Compact Resistance Model of a Three-Dimensional Via -- 4.5.1.1 Compact models of through silicon via resistance -- 4.5.1.2 Closed-form resistance model of a three-dimensional via -- 4.5.1.3 Per cent variation in resistance -- 4.5.2 Compact Inductance Model of a Three-Dimensional Via -- 4.5.2.1 Compact models of through silicon via inductance -- 4.5.2.2 Closed-form inductance model of a three-dimensional via -- 4.5.2.2.1 Inductance of equal length three-dimensional vias -- 4.5.2.2.2 Inductance of non-equal length 3-D vias -- 4.5.2.3 Per cent variation in inductance -- 4.5.3 Compact Capacitance Model of a Three-Dimensional Via -- 4.5.3.1 Compact models of through silicon via capacitance -- 4.5.3.2 Closed-form capacitance model of a three-dimensional via. |
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4.5.3.3 Per Cent variation in capacitance -- 4.5.3.4 Per Cent variation in coupling capacitance -- 4.5.4 Compact Conductance Model of a Three-Dimensional Via -- 4.5.4.1 Compact models of through silicon via conductance -- 4.6 Electrical Characterization Through Numerical Simulation -- 4.6.1 Ansys Quick Three-Dimensional Electromagnetic Field Solver -- 4.6.2 Numerical Analysis of Through Silicon Via Impedance -- 4.7 Case Study-Through Silicon Via Characterization of the MITLL TSV process -- 4.7.1 MIT Lincoln Laboratory Three-Dimensional Process -- 4.7.2 RLC Extraction of a Single Three-Dimensional Via -- 4.7.3 RLC Coupling Between Two Three-Dimensional Vias -- 4.7.4 Effects of Three-Dimensional Via Placement on Shielding -- 4.7.5 Effect of the Return Path on Three-Dimensional Via Inductance -- 4.8 Summary -- 5 Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs -- 5.1 Heterogeneous Substrate Coupling -- 5.1.1 Common Circuits and Compatible Substrate Types -- 5.1.2 Resistive Properties of Different Substrate Materials -- 5.1.3 Noise Model Reduction for Different Substrate Materials -- 5.2 Frequency Response -- 5.2.1 Isolation Efficiency of Noise Coupled System -- 5.2.2 Transfer Function of Noise Coupled System -- 5.3 Techniques to Improve Noise Isolation -- 5.3.1 Ground Network Inductance -- 5.3.2 Distance Between Aggressor and Victim -- 5.4 Summary -- 6 Three-Dimensional ICs with Inductive Links -- 6.1 Wireless On-Chip Communication Interfaces -- 6.1.1 Inductive Links -- 6.2 On-Chip Inductors for Intertier Links -- 6.2.1 Intertier Coupling Efficiency -- 6.2.2 Geometry and Electrical Characteristics of Inductor -- 6.2.3 Design Flow for Inductive Link Coils -- 6.3 Transmitter and Receiver Circuits -- 6.3.1 Design of Synchronous Inductive Link Transceivers -- 6.3.2 Asynchronous Data Transmission and Recovery -- 6.3.3 Burst Data Transmission. |
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6.4 Challenges for Wireless On-Chip Communication -- 6.4.1 Performance and Area Analysis -- 6.4.2 Crosstalk Between Inductive Links -- 6.4.3 Crosstalk Noise on Adjacent On-Chip Components -- 6.4.3.1 Crosstalk effects due to an inductive link -- 6.4.3.2 Case study -- 6.4.3.3 Crosstalk noise effects caused by inductive link arrays -- 6.4.3.4 Noise sensitivity of power network topologies -- 6.5 Intertier Power Transfer -- 6.6 Summary -- 7 Interconnect Prediction Models -- 7.1 Interconnect Prediction Models for Two-Dimensional Circuits -- 7.2 Interconnect Prediction Models for Three-Dimensional ICs -- 7.3 Projections for Three-Dimensional ICs -- 7.4 Summary -- 8 Cost Considerations for Three-Dimensional Integration -- 8.1 Through Silicon Via Processing Options -- 8.1.1 TSV Flows and Geometries -- 8.1.2 Cost Comparison of Through Silicon Via Processing Steps -- 8.1.2.1 Through silicon via lithography -- 8.1.2.2 Through silicon via silicon etch -- 8.1.2.3 Through silicon via liner processing -- 8.1.2.4 Through silicon via liner opening for through silicon via last flow -- 8.1.2.5 Through silicon via barrier and Cu seed processing -- 8.1.2.6 Through silicon via Cu plating and effect on chemical mechanical planarization -- 8.1.2.7 Through silicon via chemical mechanical planarization processing -- 8.1.2.8 Backside processing -- 8.1.3 Comparison of Through Silicon Via Processing Cost -- 8.1.3.1 Processing of the 5×50 through silicon via geometry -- 8.1.3.2 Processing of the 10×100 through silicon via geometry -- 8.1.3.3 Scaling through silicon via geometries -- 8.2 Interposer-Based Systems Integration -- 8.2.1 Cost of Interposer Manufacturing Features -- 8.2.1.1 Cost of through silicon via processing -- 8.2.1.2 Cost of die-to-die interconnect processing -- 8.2.1.3 Cost of processing metal planes and metal-insulator-metal capacitors. |
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8.2.1.4 Cost of processing microbumps and Cu pillars -- 8.2.2 Interposer Build-Up Configurations -- 8.3 Comparison of Processing Cost for 2.5-D and Three-Dimensional Integration -- 8.3.1 Components of a Three-Dimensional Stacked System -- 8.3.2 Cost of Three-Dimensional Integration Components -- 8.3.3 Comparison of Three-Dimensional System Cost -- 8.3.4 Dependence of Three-Dimensional System Cost on Active Die Size -- 8.3.5 Variation of Interposer Process Yield and Prestack Fault Coverage -- 8.4 Summary -- 9 Physical Design Techniques for Three-Dimensional ICs -- 9.1 Floorplanning Techniques -- 9.1.1 Sequence Pair Technique -- 9.2 Floorplanning Three-Dimensional ICs -- 9.2.1 Floorplanning Three-Dimensional Circuits Without Through Silicon Via Planning -- 9.2.2 Floorplanning Techniques for Three-Dimensional ICs With Through Silicon Via Planning -- 9.2.2.1 Enhanced wirelength metrics for intertier interconnects -- 9.2.2.2 Simultaneous floorplanning and through silicon via planning -- 9.2.2.3 Through silicon via planning as a post-floorplanning step -- 9.2.2.4 Practical considerations for floorplanning with through silicon via planning -- 9.2.2.5 Microarchitecture aware three-dimensional floorpanning -- 9.3 Placement Techniques -- 9.3.1 Placement Using the Force Directed Method -- 9.4 Placement in Three-Dimensional ICs -- 9.4.1 Force Directed Placement of Three-Dimensional ICs -- 9.4.2 Other Objectives in Placement Process -- 9.4.3 Analytic Placement for Three-Dimensional ICs -- 9.4.4 Placement for Three-Dimensional ICs Using Simulated Annealing -- 9.4.5 Supercell-Based Placement for Three-Dimensional Circuits -- 9.5 Routing Techniques -- 9.6 Layout Tools -- 9.7 Summary -- 10 Timing Optimization for Two-Terminal Interconnects -- 10.1 Intertier Interconnect Models -- 10.2 Two-Terminal Nets With a Single Intertier Via. |
| Subject |
Three-dimensional integrated circuits -- Design and construction.
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Integrated.
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| Added Author |
Savidis, Ioannis, author.
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Frian, Eby G., author.
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| Other Form: |
Erscheint auch als: Druck-Ausgabe 9780124105010 |
| ISBN |
9780124104846 (electronic bk.) |
|
0124104843 (electronic bk.) |
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9780124105010 |
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0124105017 |
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9780124105010 |
| Standard No. |
C20120069347 |
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9780124104846 |
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(WaSeSS)ssj0001873675 |
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AU@ 000061153956 |
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CHBIS 011069439 |
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CHNEW 001014410 |
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CHVBK 499782526 |
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GBVCP 1004856288 |
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GBVCP 897845412 |
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DKDLA 820120-katalog:9910110328105765 |
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