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Author Radecka, Katarzyna.

Title Verification by error modeling [electronic resource] : using testing techniques in hardware verification / written by Katarzyna Radecka, Zeljko Zilic.

Imprint Boston : Kluwer Academic Publishers, 2003.

Copies

Location Call No. OPAC Message Status
 Axe ProQuest E-Book  Electronic Book    ---  Available
Description xiv, 216 p. : ill.
Series Frontiers in electronic testing ; 25
Frontiers in electronic testing ; 25.
Bibliography Includes bibliographical references and index.
Reproduction Electronic reproduction. Ann Arbor, MI : ProQuest, 2015. Available via World Wide Web. Access may be limited to ProQuest affiliated libraries.
Subject Integrated circuits -- Very large scale integration -- Computer-aided design.
Integrated circuits -- Verification.
Error analysis (Mathematics)
Genre/Form Electronic books.
Added Author Zilic, Zeljko.
ProQuest (Firm)
ISBN 1402076525 (alk. paper)

 
    
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