| Description |
1 online resource (xxx, 777 pages) : illustrations |
|
text txt rdacontent |
|
computer c rdamedia |
|
online resource cr rdacarrier |
| Series |
The Morgan Kaufmann series in systems on silicon |
|
Morgan Kaufmann series in systems on silicon.
|
| Bibliography |
Includes bibliographical references and index. |
| Contents |
Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. |
| Summary |
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. |
| Note |
Print version record. |
| Subject |
Integrated circuits -- Very large scale integration -- Testing.
|
|
Integrated circuits -- Very large scale integration -- Design.
|
|
Integrated circuits -- Very large scale integration -- Design and construction.
|
|
Circuits intégrés à très grande échelle -- Essais.
|
|
Circuits intégrés à très grande échelle -- Conception et construction.
|
|
TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- VLSI & ULSI.
|
|
TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Logic.
|
|
COMPUTERS -- Logic Design.
|
|
Integrated circuits -- Very large scale integration -- Testing.
|
|
Integrated circuits -- Very large scale integration -- Design.
|
|
Integrated circuits -- Very large scale integration -- Design and construction
|
|
Integrated circuits -- Very large scale integration -- Design
|
|
Integrated circuits -- Very large scale integration -- Testing
|
|
Testen
|
|
VLSI
|
|
Circuitos integrados vlsi.
|
| Genre/Form |
dissertations.
|
|
Academic theses
|
|
Academic theses.
|
|
Thèses et écrits académiques.
|
| Added Author |
Wang, Laung-Terng, editor.
|
|
Wu, Cheng-Wen, EE Ph. D., editor.
|
|
Wen, Xiaoqing, editor.
|
| Other Form: |
Print version: VLSI test principles and architectures. Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, ©2006 0123705975 9780123705976 (DLC) 2006006869 (OCoLC)64624834 |
| ISBN |
9780080474793 (electronic bk.) |
|
0080474799 (electronic bk.) |
|
9780123705976 (hbk.) |
|
0123705975 (hbk.) |
| Standard No. |
AU@ 000043319312 |
|
AU@ 000051860547 |
|
AU@ 000067090649 |
|
CHNEW 001006392 |
|
DEBBG BV039832118 |
|
DEBBG BV042307512 |
|
DEBBG BV043044400 |
|
DEBBG BV044123115 |
|
DEBSZ 355395088 |
|
DEBSZ 367756056 |
|
DEBSZ 422214760 |
|
DEBSZ 43038047X |
|
DEBSZ 449091201 |
|
GBVCP 785350373 |
|
HEBIS 291468322 |
|
NZ1 12434945 |
|
NZ1 14540149 |
|
